1. Field of the Invention
The present invention relates to a column decoder of a semiconductor memory device and more particularly, to a column decoder of a synchronous dynamic random access memory (SDRAM) that activates a corresponding column select line (CSL) in response to a column address signal.
2. Description of the Related Art
Semiconductor memory devices, such as SDRAMs, have a column decoder, which receives a read or write command and activates a CSL designated by a column address signal in synchronization with a clock signal. As the densities of SDRAMs increase, the capacities of memory cell arrays of the SDRAMs increase, and the sizes and separations of circuit elements decrease. Hence, the resistance and the capacitance of a CSL considerably increase, and thus the size of a driver in a column decoder must be increased to drive the CSL, resulting in an increase in the chip size of the SDRAM or a reduction in the speed of the SDRAM.
Increasing a driver size in a column decoder has been an effective method for driving the CSL in low density SDRAM devices. However, increasing the processing speed in DRAMs of 256 Mbit or more than 1 Gbit is difficult even though the size of a driver is increased.
An aspect of the present invention provides a column decoder that can improve the processing speed of a semiconductor memory device while avoiding the chip size increase of the device. An embodiment of the column decoder includes a column select line driver having a NAND gate. The NAND gate performs a NAND operation with a column select line enable signal and an output signal of a sub-predecoder generated in response to a column address signal, and provides the output signal to the selected column select line.
The column select line driver including the NAND gate is smaller than a conventional column select line driver including a NOR gate, thereby reducing the chip size of the memory device and decreasing a logic delay and a load.